Method and system for map-free inspection of semiconductor devices

ABSTRACT

A system and method for defect detection in a hole array on a substrate is disclosed herein. In one embodiment, a method for defect detection in a hole array on a substrate, includes: scanning a substrate surface using at least one optical detector, generating at least one image of the substrate surface; and analyzing the at least one image to detect defects in the hole array on the substrate surface based on a set of predetermined criteria.

BACKGROUND

In the semiconductor integrated circuit (IC) industry, there is acontinuing demand for smaller device dimensions and higher circuitpacking densities. This demand has driven the semiconductor industry todevelop new materials and complex processes. Manufacturing an IC at suchdimensions and complexity generally uses advanced techniques to inspectthe IC at various stages of the manufacturing process for qualitycontrol purposes.

For example, when a feature (e.g., a gate/drain/source feature of atransistor, a horizontal interconnect line, or a vertical via, etc.) isto be formed on a wafer, the wafer typically goes through a productionline which comprises multiple processing stations typically usingdifferent process tools to perform various operations such as cleaning,photolithography, dielectric deposition, dry/wet etching, and metaldeposition, for example. Prior to being transferred to a next step(e.g., a next processing station) in the production line, the wafer istypically inspected for defects.

Currently, such defect inspection, which is manually performed by ahuman using an optical instrument to determine the scanning alignmentand the presence of defect, is time-consuming resulting a low yield.Despite this long felt need, no suitable systems meeting theserequirements are available.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that various features are not necessarily drawn to scale. In fact,the dimensions and geometries of the various features may be arbitrarilyincreased or reduced for clarity of illustration.

FIG. 1A illustrates a block diagram of a system integrating a pluralityof inline inspection systems into a semiconductor manufacturingproduction line, in accordance with some embodiments of the presentdisclosure.

FIG. 1B illustrates a schematic of an inspection system for scanning asurface, in accordance with some embodiments.

FIG. 2A illustrates a perspective view of an inspection system, inaccordance with some embodiments.

FIG. 2B illustrates a perspective view of an inspection system, whichincludes a reflective mirror, in accordance with some embodiments.

FIG. 2C illustrates a perspective view of an inspection system, whichincludes a reflective mirror, in accordance with some embodiments.

FIG. 2D illustrates a perspective view of an inspection system, whichincludes a reflective mirror, in accordance with some embodiments.

FIGS. 3A-3C illustrate perspective views of a system for scanning asubstrate surface while the substrate is transferred by a conveyorthrough a field of view of a line scan camera, in accordance with someembodiments of the present disclosure.

FIG. 4 illustrates a block diagram of an inspection system for scanninga surface of a wafer, in accordance with some embodiments of the presentdisclosure.

FIG. 5 illustrates a flowchart of a method of defection inspection of asubstrate surface, in accordance with some embodiments of the presentdisclosure.

FIGS. 6A-6E illustrate schematics of a hole feature during apost-processing analysis, in accordance with some embodiments of thepresent disclosure.

FIG. 7 illustrates a user interface of a software program that is usedfor post-processing surface images, in accordance with some embodimentsof the present disclosure.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

The following disclosure describes various exemplary embodiments forimplementing different features of the subject matter. Specific examplesof components and arrangements are described below to simplify thepresent disclosure. These are, of course, merely examples and are notintended to be limiting. For example, it will be understood that when anelement is referred to as being “connected to” or “coupled to” anotherelement, it may be directly connected to or coupled to the otherelement, or one or more intervening elements may be present.

The presented disclosure provides various embodiments of a method andsystem for defect inspection in a hole array on a substrate. In contrastto the traditional scanning method, a system and method does not requiremanual alignment and provides flexibility in detecting defects in holearrays with different physical geometries and configurations.Accordingly, the above-mentioned issues may be advantageously avoided.

This description of the exemplary embodiments is set to be understood inconnection with the figures of the accompanying drawing, which are to beconsidered part of the entire written description. In the description,relative terms such as “lower,” “upper,” “horizontal,” “vertical,”“above,” “below,” “up,” “down,” “top” and “bottom” as well asderivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,”etc.) should be construed to refer to the orientation as then describedor as shown in the drawing under discussion. These relative terms arefor convenience of description and do not require that the apparatus beconstructed or operated in a particular orientation.

FIG. 1 illustrates a block diagram of a system 100 integrating aplurality of inline inspection systems into a semiconductormanufacturing production line according to one or more embodiments ofthe present disclosure. It is noted that the system 100 is merely anexample, and is not intended to limit the present disclosure.Accordingly, it is understood that additional operations may be providedbefore, during, and after the system 100 of FIG. 1 , and that some otheroperations may only be briefly described herein.

Referring to FIG. 1 , the system 100 comprises a plurality of processingstations 102 a, 102 b and up to 102 c (collectively referred to asprocessing station(s) 102 herein), a plurality of inspection systems 104a and 104 b (collectively referred to as inspection system(s) 104herein) located between respective processing stations 102, and aplurality of stockers 106 a and 106 b (collectively referred to hasstocker(s) 106 herein) coupled to respective inspection systems 104.Examples of IC manufacturing processes conducted in processing stations102 include cleaning, photolithography, wet etching, dry etching,dielectric deposition, metal deposition, and any processes known in theart. At least one feature can be created in each processing station 102including a metal contact, an etch trench, an isolation, a via, aninterconnect line and the like. In some embodiments, the at least onefeature includes a hole.

At least two processing stations 102 are coupled to an intermediateinspection system 104, in which at least one wafer from one priorprocessing station 102 can be inspected before it is transported to thenext processing station 102. For example, a processing station 102 b iscoupled to a prior processing station 102 a through an inspection system104 a and is also coupled to a later processing station 102 c through aninspection system 104 b. At least one stocker 106 is coupled to eachinspection system 104. For example, a stocker 106 a is coupled to theinspection system 104 a, in which a wafer with defects as determined bythe inspection system 104 a can be extracted from the production lineand stored in the stocker 106 a for reprocessing or rejection, insteadof being transferred to the next processing station 102 b.

As discussed in further detail below, in some embodiments, theinspection system 104 includes a wafer transport system (e.g., aconveyor) that transfers a wafer through the inspection station, a linescan camera, and a local computer with a storage unit and a displayunit. For example, the wafer can be transferred on a conveyor in theinspection system 104 a from processing station 102 a to processingstation 102 b, or if a defect is detected to respective stocker 106 a.While being transferred in the inspection system 104 a, the surface ofthe wafer is imaged by the line scan camera. Data collected by the linescan camera can be stored in a storage unit of a local computer 112 afollowed by a preprocessing step. Examples of preprocessing can includereconstruction of the line images into a two-dimensional image of thewafer surface and various distortion corrections, as described infurther detail below. As shown in FIG. 1 , a second local computer 112 bis coupled to the second inspection system 104 b to store and preprocessdata collected by the second inspection system 104 b.

Each of the local computers 112 a and 112 b are generally orcollectively referred to as local computer(s) 112 herein. The localcomputers 112 are each coupled to a remote computer resource 110 througha connection 108. In some embodiments, the connection 108 may include aEthernet cable, an optical fiber, a wireless communication media, and/orother networks known in the art. It should be understood that otherconnections and intermediate circuits can be deployed between the localcomputers 112 and the remote computer resource 110 to facilitateinterconnection.

In some embodiments, an image processing operation can be performed bythe remote computer resource 110 to automatically compare designcriteria with the collected image of the wafer surface in accordancewith predetermined algorithms or rules concerning, e.g., diameter,roundness, raw edge, consumption, contamination, and the like. In someembodiments, the remote computer resource 110 includes a computernetwork, servers, applications, and/or data centers, generally known asthe “cloud” or cloud computing. Results and decisions from the remotecomputer resource 110 about whether the wafer contains defects areprocessed and transmitted back to the local computer 112 associated witha respective inspection system 104 through the connection 108. In someembodiments, the remote computer resource 110 may be unnecessary if thelocal computer 112 can perform the image processing and analysislocally. In some embodiments, various inspection results (e.g.,diameter, roundness, raw edge, consumption, and contamination, overlaidwith design patterns) are displayed on a local display unit and, if thewafer is determined to be defective, a control signal is sent to theconveyor to transfer the wafer to a respective stocker 106. In someembodiments, a wafer that fails to meet a pre-defined threshold orcriterion, and thus determined to be defective, is transferred by theconveyor in the inspection system 104 a to a cassette in the stocker 106a for reprocessing or rejection. On the other hand, if the wafer isdetermined to be not defective meeting the pre-defined threshold orcriterion, then it is transferred by the conveyor to the next processingstation 102 b for further processing. In some embodiments, the thresholdmay vary depending on the application and can be set by manufacturers.

Although the system 100 in the illustrated embodiment of FIG. 1 includesonly three processing stations 102, two inspection systems 104, twostockers 106, two local computers 112 and one remote computer 110, it isunderstood that the illustrated embodiment of FIG. 1 is merely providedfor illustration purposes. The system 100 may include any desired numberof processing stations 102 with any desired number of inspection systems104 and stocker 106 while remaining within the scope of the presentdisclosure. Furthermore, in some embodiments, an inspection system 104can be coupled to two or more processing stations 102 and/or two or morestockers 106. In some embodiments, two or more inspection systems 104may be located between two processing stations 102.

In some embodiments, a separate transfer chamber in the inspectionstation 104 can be coupled to a process chamber in the processingstation 102. In some embodiments, for processes such as metal ordielectric deposition, for example, the inline camera of the inspectionsystem 104 is separated from the deposition chamber of the processingstation to protect the camera and other components of the inspectionsystem 104 from deposition of materials, or extreme conditions, e.g.,high temperature heating and ion bombardment. In some embodiments, thetransfer chamber of the inspection system 104 can maintain a vacuum sealbetween two vacuum process chambers or purged with high purity inert gas(e.g., Ar and N₂) to provide an inert atmosphere for air sensitivewafers during the transferring process. In some embodiments, theinspection system 104 may be configured inside the process chamber ofthe processing station 102, if the process does not interfere with theinspection. Such an integration of inspection systems to an existingsemiconductor manufacturing production line provides an inlineinspection that can efficiently detect and map the defects of entirewafer, without relying on manual inspection or statistical sampling ofthe wafer surface. By mapping the defects of the wafer after eachprocessing stage, as part of the inline manufacturing process, criticalinsights into process characteristics (e.g., tools and conditions) ofeach stage can be obtained while minimizing adverse effects onthroughput.

FIG. 1B illustrates a schematic of an inspection system 104 for scanninga surface, in accordance with some embodiments. The inspection system104 comprises a pair of tracks 122A and 122B that guide a movement of anoptical detector 130 in a first horizontal direction (i.e.,X-direction), and a track 124 that guides a movement of the opticaldetector 130 in a second horizontal direction (i.e., Y-direction) thatis normal to the first horizontal direction (e.g., X-direction). In someembodiments, the optical detector 130 is a line scan camera. The X-Yplane can be parallel to the plane of a stage 132, on which a part to beinspected can be placed. Motors 126 and 128 provide linear movements inthe X- and Y-direction such that the optical detector 130 in the X-Yplane can scan the surface of a wafer (not shown) on the stage 132. Insome embodiments, the optical detector 130 can also move in a thirdvertical direction (e.g., Z-direction) that is perpendicular to the X-Yplane on a track 134 controlled by a motor 126. In some embodiments, themotors 126, 128, and 136 can be linear electric motors providing highspeed linear motion and accurate position control of the opticaldetector 130. In some embodiments, a plurality of optical detectors 130can be used to scan complex surfaces to simultaneously scan multiplewafers or multiple locations on a same surface. In some otherembodiments, the wafer under inspection can be moved on a conveyorstage/a robot arm, while the optical detector 130 is fixed.

As mentioned above, FIGS. 2A-2C illustrate a variety of perspectiveviews of an inspection system 200, in accordance with some embodimentsof the present disclosure. These are, of course, merely examples and arenot intended to be limiting.

FIG. 2A illustrates a perspective view of an inspection system 200, inaccordance with some embodiments. In one embodiment, a wafer 206 issecured by a suitable wafer holder 208 coupled to a conveyor, e.g., amotorized robotic transfer arm 210. The robotic transfer arm 210 istranslatable in both the X and Y directions. In some embodiments, therobotic transfer arm 210 is also rotatable about a certain center in theX-Y plane. In the illustrated embodiment, the wafer holder 208 coupledto the robotic transfer arm 210 transfers the wafer 206 along the X axisat a constant speed during scanning.

In the embodiment shown in FIG. 2A, a line scan camera 202 with animaging lens 203 is mounted on a frame 204 located at a certain workingdistance 209 from the surface of the wafer 206 in the vertical (Z)direction. In some embodiments, these three parts, i.e., 202, 203 and204, are stationary. In some embodiments, a diffused illumination from aremotely located light source (not shown) can be used, which can providesufficient light for the line scan camera 202 to capture high-resolutionimages of the wafer 206. In some embodiments, the position of the frame204 and the line scan camera 202 relative to the wafer 106 can beadjusted for alignment purpose.

In some embodiments, instead of capturing an image of the entire waferas a whole, the line scan camera 202 collects image data one scan lineat a time. An image line 212, indicated by a short dashed line in FIG.2A, is a line region where the reflected or scattered light from thesurface of the wafer under inspection is collected by a light sensor inthe line scan camera 202 through the imaging lens 203. In someembodiments, the field of view 218 of the line scan camera 202 in the Ydirection, e.g., the maximum length of the image line 212, can beadjusted by the width of the light sensor in the line scan camera 202,the working distance 209, and the focal length of the lens 203. In someembodiments, the image line 212 is the overlap portion of the field ofview 218 in Y direction and the surface of the wafer 206. For example,the width of imaging lens can be 25 millimeters (mm), which can providea field of view 218 with a width of up to 215 mm in the Y direction anda sensor width of 14 mm. Therefore, the resolution in the Y direction,which has a unit in mm per pixel for a light sensor width of 1024 pixelsper line, can be controlled by the working distance 209 taking intoaccount the diameter of the wafer 206. In some other embodiments, theline scan cameras comprising light sensors with different width andnumbers of pixels can be used and are within the scope of thisdisclosure. In some embodiments, the resolution that such system canprovide is 9 micrometer.

In some embodiments, the line scan camera 202 includes a light sensorthat can be based on a variety of technologies such as, for example, acharge-coupled detector (CCD), a complementary metal-oxide-semiconductor(CMOS), or a hybrid CCD/CMOS architecture. In some embodiments, thelight sensor can be a mono or color sensor. In some embodiments, suchlight sensor can be configured to either work in a broad range ofwavelengths or a narrow range of wavelengths e.g., ultraviolet light,visible light, infrared light, x-ray and/or other appropriatewavelengths. In some other embodiments, such light sensor can beconfigured to receive either reflected and/or scattered non-fluorescencelight from a light source or a fluorescence light emitted by the defectsor features due to an excitation by the light source.

In some embodiments, the wafer 206 includes a silicon substrate.Alternatively, the wafer 206 may include other elementary semiconductormaterial such as, for example, germanium. The substrate may also includea compound semiconductor material such as silicon carbide, galliumarsenide, indium arsenide, and indium phosphide. Furthermore, the wafer206 may include an alloy semiconductor material such as silicongermanium, silicon germanium carbide, gallium arsenic phosphide, andgallium indium phosphide. Each material may interact differently withthe incident light from the light source due to different materialproperties, e.g., refractive index and extinction coefficient, which canaffect the design of the illumination source and the light sensor, e.g.,wavelength, sensitivity and mode (e.g., scattered, reflected light orfluorescence light), as well as the speed of the conveyor.

The wafer 206 may contain at least one feature to be opticallyinspected. In some embodiments, the wafer 206 may include trenches fromdry/wet etching of a dielectric material including fluorinated silicaglass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass(BPSG), polyimide, and/or other future developed low-k dielectricmaterials. In some embodiments, the wafer 206 can also includeconductive features such as, for example horizontal interconnect linesor vertical vias from processes like chemical vapor deposition (CVD),physical vapor deposition (PVD), spin-on coating and the like. In someembodiment, the design of the illumination source, light sensor, andimaging lens 203 can be also affected by the physical dimension of thesematerials on the wafer 206, e.g., thickness and roughness, incombination with the material property of the wafer 206 and thematerials on top, due to phenomena such as, for example interferenceeffect and antireflection effect.

FIG. 2B illustrates a perspective view of an inspection system 200, inaccordance with some embodiments of the present disclosure. In someembodiments, a reflective mirror 214 can reflect the non-fluorescentlight and/or the fluorescent light from the image line 212 on thesurface of the wafer 206 to the light sensor in the line scan camera 202through lens 203. Since the optical pathway can be folded with a portionin the X direction parallel to the transfer direction of the wafer 206,the use of the reflective mirror 214 can allow the use of inspectionsystem 200B in applications where a large space in the Z direction isnot available, e.g., the total height of a transfer chamber is smallerthan the summation of the working distance 109 and the length of theline scan camera 102. In some embodiments, the position in the X-Z planeand the tilt angle (i.e., rotation) along the Y axis of the reflectivemirror 114 can be adjusted for alignment purpose. The configurationpresented in FIG. 2B is merely for illustration purpose and is notintended to be limiting. For example, a plurality of reflective mirrorscan be used to provide a desired optical path in order to direct thelight to a desired direction. In some embodiments, the reflective mirror214 is flat to prevent distortion of reflected light caused by thesurface of the reflective mirror 214. For example, the reflective mirror214 comprises a surface corrugation level in a range less than or equalto 20 micron/20 millimeter (μm/mm) and a surface curvature in a rangeequal to or less than 0.1 mm/100 mm.

FIG. 2C illustrates a perspective view of an inline inspection system200, in accordance with some embodiments of the present disclosure. Insome embodiments, the light sensor in the line scan camera 202, theworking distance 209, and the imaging lens 203 can be configured toassure the width of the field of view 218 in the Y direction is equal orgreater than the diameter of the wafer 206. In some embodiments, thewafer 206 can be transported on a pair of tracks 220, as shown in FIG.2C.

Because of the requirement for a wide field of view 218, when a largewafer is inspected especially within a limited space, a uniformintensity from a flood light source illumination becomes difficult. Asmentioned above, since the image line 212 is the only portion of thewafer that needs to be uniformly illuminated for collecting line-scanimages by the line scan camera 202, the illumination to the image line212 can be from a line light source 230 having a narrow slit to direct alight beam. In some embodiments, the line light source 230 can includean array of light emitting diodes (LEDs) with a half bar converging linelens as an optical guide. Such a light source may be configured in thelimited space while maintaining a uniform illumination to the image line212 on the wafer 206. However, in accordance with various embodiments,various light sources suitable for various applications may be utilized.In another embodiment, an imaging lens 203 with a larger diameter, asmaller focal length, and/or a large refractive index can be used toprovide a wide field of view 218 at a small working distance 209. Toobtain a comparable resolution (mm per pixel) to that on a smallerwafer, a camera with a larger sensor size may be used. In someembodiments, the optical pathway can be redirected by a reflectivemirror or a plurality of reflective mirrors e.g., an array of reflectivemirrors (not shown) to accommodate the inspection system in certainapplications.

FIG. 2D illustrates a perspective view of an inline inspection system200, in accordance with some embodiments of the present disclosure. Insome embodiments, a plurality of line scan cameras 202 are used to scanthe same surface of a wafer 206 with a large diameter. In someembodiments, the wafer 206 can be transported on a pair of tracks 220,as shown in FIG. 2D. In some embodiments, each of the plurality ofoptical detector 202 is configured to scan a portion of the surface ofthe wafer 206. In some embodiments, a plurality of line scan images fromeach of the plurality of line scan cameras 202 are the merged togetherusing the position information of the wafer 206 based on a preconfiguredalgorithm.

In some embodiments, the relative position between the line scan camera202 and the light source 230 can affect the inspection criteria. Forexample, in case of using a linear light source 230 on a wafer 206 witha reflective surface, when the line scan camera 202 is off the angle ofreflection, the reflective surface appears dark in the light sensorwhile the features and/or defects can scatter light and appear bright inthe image. For another example, when the line scan camera 202 is withinthe angle of reflection of the incident light from the light source 230,the surface appears bright while the features and/or defects may appeardarker or brighter depending on their reflectivity relative to the restof the surface.

In some embodiments, the conveyor can be a transfer robot which consistsof multiple joints, a single arm, and a stage. In some embodiments, thetransfer robot can provide high-speed and high-accuracy wafer handlingwithin a limited space. As discussed above, a surface inspection usingthe line scan camera 202 requires a linear motion of the wafer 206 in adirection perpendicular to the axis of the image line 212. In someembodiments, the inline inspection system 200 with the line scan camera202 can be configured to focus on one portion of a wafer transferpathway where such linear relative motion between the wafer 206 and theimage line 212 can be provided by a combination of moving parts of thetransfer robot (e.g., rotation of joints and linear motion of arm andthe stage).

In some embodiments, such inspection system can be combined with otherfunctional inspection processes either inline or offline for additionalfunction yield tests, e.g., electrical conductivity measurements.Although the above-illustrated inline defect detection system includesonly one line scan camera (e.g., 202 in FIGS. 2A-2D), any desired numberof line scan cameras can be combined in the inspection system, e.g.,working in different ranges of wavelength and simultaneously detectdifferent defects (e.g., size, distribution, and materials), whileremaining within the scope of the present disclosure.

FIGS. 3A-3C illustrate perspective views of a system 300 for scanning asubstrate surface while the substrate is transferred by a conveyorthrough a field of view of a line scan camera, in accordance with someembodiments of the present disclosure.

The system 300 first scans the wafer 206 at a first position 250 of thewafer 206 controlled by the conveyor 208/210, as shown in FIG. 3A. Inthe first position 250, the scan of the wafer surface is initiated, inaccordance with some embodiments. As the wafer 206 enters the field ofview 218 in Y direction, a recording cycle of a line scan image from theline scan camera 202 by a local computer 220 is initiated. In someembodiments, the recording can be also initiated by a position signalfrom an encoder that is located on a motor of the robotic transfer arm210. In some embodiments, image data as the scanning progresses is shownon a display monitor 222 coupled to the local computer 220. As shown inFIG. 3A, at the beginning of the scanning process, no image data is yetavailable for display on the display monitor 222.

In some embodiments, such recording process of one single line of pixelfrom the line scan camera 202 to the local computer 220 is conducted intwo steps, i.e., exposure and readout steps. In some embodiments, therecording process of a plurality of lines of pixels from the line scancamera 202 is conducted. In the first step, the line scan camera 202collects a single line of pixels per exposure at one position which isinitiated by the application of a trigger pulse to the camera, asdiscussed above. The trigger pulse also ends the exposure period andstarts the second step of transferring the sensor image information to areadout register and finally out of the camera to the local computer, tocomplete the readout step. In some embodiments, the sensor imageinformation is provided to the local computer 220 one line of pixels ata time. In some other embodiments, the line scan camera 202 collects aplurality of line of pixels per exposure at one position.

In some embodiments, the exposure time of an individual line at theimage line 212 and the number of lines can be affected by the velocityof the wafer 206 and resolution requirement along the X axis in thewafer plane. In some embodiment, the exposure time may also be affectedby illumination intensity, sensitivity of the light sensor, and type ofdefects being detected. In parallel with the first readout period, theline scan camera 202 continues with the next exposure step in a nextcycle, while the robotic transfer arm 210 moves the wafer 206 to thenext position.

The system 300 continues a second position 251 where a partial scan ofthe wafer surface of interest is completed, as shown in FIG. 3B, inaccordance with some embodiments. In some embodiments, reconstruction ofthe image of the wafer surface under inspection is conducted based on aplurality of single line images through the local computer 220 and thesurface image is then displayed on the display unit 222 in real time, asshown in FIG. 3B.

Once the surface of the wafer under inspection has been completelyscanned at a third position 252, as illustrated in FIG. 3C, the localcomputer 220 then proceeds to reconstruct and preprocess the completetwo-dimensional surface image to prepare the image for defect detection.In some embodiments, such preprocessing of the surface image includesoffset correction, gain correction, distortion correction, adjustingcontrast, and the like. In accordance with some embodiments, thereconstructed image is displayed on the display unit 222, as shown inFIG. 3C.

FIG. 4 illustrates a block diagram of an inspection system 400 forscanning a surface of a wafer, in accordance with some embodiments ofthe present disclosure. In the illustrated embodiment, the system 400comprises at least one line scan camera 402, a plurality of motors 404that can control the movement of the line scan camera in the X-Ydirection as shown in FIG. 1 or the wafer in the X-Y direction as shownin FIGS. 2A-2D. An additional motor 404 can be used for the adjustmentof the position of the line scan camera 402 in the Z-direction, inaccordance with some embodiments, to accommodate the use of themechanical system with different detectors with different field of viewor working distances. At least one decoder 406 is installed on aplurality of tracks to provide position data. In some embodiments, atleast one trigger sensor 408 can be also used to trigger a scan. In someembodiments, a digital camera can be also used to guide the positioningof the line scan camera 402 to the position such as a starting point oran area of interest.

A controller 410 in the system 400 for scanning a surface is arepresentative device and may comprise a processor 410A, a memory 410B,an input/output interface 410C (hereinafter “I/O interface”), acommunications interface 410D, and a system bus 410E. In someembodiments, components in the controller 410 in the system 400 may becombined or omitted such as, for example, not including thecommunications interface 410D. In some embodiments, the controller 410of the system 400 may comprise other components not combined orcomprised in those shown in FIG. 4 . For example, the controller 410 ofthe system 400 also may comprise a power subsystem providing power tothe light source. In other embodiments, the controller 410 of the system400 may comprise several instances of the components shown in FIG. 4 .

The processor 410A may comprise any processing circuitry operative tocontrol the operations and performance of the controller 410 of thesystem 400. In various aspects, the processor 410A may be implemented asa general purpose processor, a chip multiprocessor (CMP), a dedicatedprocessor, an embedded processor, a digital signal processor (DSP), anetwork processor, an input/output (I/O) processor, a media accesscontrol (MAC) processor, a radio baseband processor, a co-processor, amicroprocessor such as a complex instruction set computer (CISC)microprocessor, a reduced instruction set computing (RISC)microprocessor, and/or a very long instruction word (VLIW)microprocessor, or other processing device. The processor subsystem 406also may be implemented by a controller, a microcontroller, anapplication specific integrated circuit (ASIC), a field programmablegate array (FPGA), a programmable logic device (PLD), and so forth.

In various aspects, the processor 410A may be arranged to run anoperating system (OS) and various applications. Examples of an OScomprise, for example, operating systems generally known under the tradename of Apple OS, Microsoft Windows OS, Android OS, and any otherproprietary or open source OS. Examples of applications comprise, forexample, a telephone application, a camera (e.g., digital camera, videocamera) application, a browser application, a multimedia playerapplication, a gaming application, a messaging application (e.g., email,short message, multimedia), a viewer application, and so forth.

In some embodiments, at least one non-transitory computer-readablestorage medium is provided having computer-executable instructionsembodied thereon, wherein, when executed by at least one processor, thecomputer-executable instructions cause the at least one processor toperform embodiments of the methods described herein. Thiscomputer-readable storage medium can be embodied in the memory 410B.

In some embodiments, the memory 410B may comprise any machine-readableor computer-readable media capable of storing data, including bothvolatile/non-volatile memory and removable/non-removable memory. Thememory 410B may comprise at least one non-volatile memory unit. Thenon-volatile memory unit is capable of storing one or more softwareprograms. The software programs may contain, for example, applications,user data, device data, and/or configuration data, or combinationstherefore, to name only a few. The software programs may containinstructions executable by the various components of the controller 410of the system 400.

For example, memory 410B may comprise read-only memory (ROM),random-access memory (RAM), dynamic RAM (DRAM), Double-Data-Rate DRAM(DDR-RAM), synchronous DRAM (SDRAM), static RAM (SRAM), programmable ROM(PROM), erasable programmable ROM (EPROM), electrically erasableprogrammable ROM (EEPROM), flash memory (e.g., NOR or NAND flashmemory), content addressable memory (CAM), polymer memory (e.g.,ferroelectric polymer memory), phase-change memory (e.g., ovonicmemory), ferroelectric memory, silicon-oxide-nitride-oxide-silicon(SONOS) memory, disk memory (e.g., floppy disk, hard drive, opticaldisk, magnetic disk), or card (e.g., magnetic card, optical card), orany other type of media suitable for storing information.

In one embodiment, the memory 410B may contain an instruction set, inthe form of a file for executing a method of generating one or moretiming libraries as described herein. The instruction set may be storedin any acceptable form of machine readable instructions, includingsource code or various appropriate programming languages. Some examplesof programming languages that may be used to store the instruction setcomprise, but are not limited to: Java, C, C++, C#, Python, Objective-C,Visual Basic, or .NET programming. In some embodiments a compiler orinterpreter is comprised to convert the instruction set into machineexecutable code for execution by the processor 410A.

In some embodiments, the I/O interface 410C may comprise any suitablemechanism or component to at least enable a user to provide input to thecontroller 410 and the controller 410 to provide output to the user. Forexample, the I/O interface 410C may comprise any suitable inputmechanism, including but not limited to, a button, keypad, keyboard,click wheel, touch screen, or motion sensor. In some embodiments, theI/O interface 410C may comprise a capacitive sensing mechanism, or amulti-touch capacitive sensing mechanism (e.g., a touch screen).

In some embodiments, the I/O interface 410C may comprise a visualperipheral output device for providing a display visible to the user.For example, the visual peripheral output device may comprise a screensuch as, for example, a Liquid Crystal Display (LCD) screen,incorporated into the controller 410 of the system 400. As anotherexample, the visual peripheral output device may comprise a movabledisplay or projecting system for providing a display of content on asurface remote from the controller 410 of the system 400. In someembodiments, the visual peripheral output device can comprise acoder/decoder, also known as a Codec, to convert digital media data intoanalog signals. For example, the visual peripheral output device maycomprise video Codecs, audio Codecs, or any other suitable type ofCodec.

The visual peripheral output device also may comprise display drivers,circuitry for driving display drivers, or both. The visual peripheraloutput device may be operative to display content under the direction ofthe processor 410A. For example, the visual peripheral output device maybe able to play media playback information, application screens forapplication implemented on the controller 410 of the topological scansystem 400, information regarding ongoing communications operations,information regarding incoming communications requests, or deviceoperation screens, to name only a few.

In some embodiments, the communications interface 410D may comprise anysuitable hardware, software, or combination of hardware and softwarethat is capable of coupling the controller 410 of the system 400 to oneor more networks and/or additional devices (such as, for example, theoptical detector 242, motor 404, decoder 406, and trigger sensor 408).The communications interface 410D may be arranged to operate with anysuitable technique for controlling information signals using a desiredset of communications protocols, services or operating procedures. Thecommunications interface 410D may comprise the appropriate physicalconnectors to connect with a corresponding communications medium,whether wired or wireless.

Systems and methods of communication comprise a network, in accordancewith some embodiments. In various aspects, the network may compriselocal area networks (LAN) as well as wide area networks (WAN) includingwithout limitation Internet, wired channels, wireless channels,communication devices including telephones, computers, wire, radio,optical or other electromagnetic channels, and combinations thereof,including other devices and/or components capable of/associated withcommunicating data. For example, the communication environments comprisein-body communications, various devices, and various modes ofcommunications such as wireless communications, wired communications,and combinations of the same.

Wireless communication modes comprise any mode of communication betweenpoints (e.g., nodes) that utilize, at least in part, wireless technologyincluding various protocols and combinations of protocols associatedwith wireless transmission, data, and devices. The points comprise, forexample, wireless devices such as wireless headsets, audio andmultimedia devices and equipment, such as audio players and multimediaplayers, telephones, including mobile telephones and cordlesstelephones, and computers and computer-related devices and components,such as printers, network-connected machinery such as a circuitgenerating system 404, and/or any other suitable device or third-partydevice.

Wired communication modes comprise any mode of communication betweenpoints that utilize wired technology including various protocols andcombinations of protocols associated with wired transmission, data, anddevices. The points comprise, for example, devices such as audio andmultimedia devices and equipment, such as audio players and multimediaplayers, telephones, including mobile telephones and cordlesstelephones, and computers and computer-related devices and components,such as printers, network-connected machinery, and/or any other suitabledevice or third-party device. In various implementations, the wiredcommunication modules may communicate in accordance with a number ofwired protocols. Examples of wired protocols may comprise UniversalSerial Bus (USB) communication, RS-232, RS-422, RS-423, RS-485 serialprotocols, FireWire, Ethernet, Fiber Channel, MIDI, ATA, Serial ATA, PCIExpress, T-1 (and variants), Industry Standard Architecture (ISA)parallel communication, Small Computer System Interface (SCSI)communication, or Peripheral Component Interconnect (PCI) communication,to name only a few examples.

Accordingly, in various aspects, the communications interface 410D maycomprise one or more interfaces such as, for example, a wirelesscommunications interface, a wired communications interface, a networkinterface, a transmit interface, a receive interface, a media interface,a system interface, a component interface, a switching interface, a chipinterface, a controller, and so forth. When implemented by a wirelessdevice or within wireless system, for example, the communicationsinterface 410D may comprise a wireless interface comprising one or moreantennas, transmitters, receivers, transceivers, amplifiers, filters,control logic, and so forth.

In various aspects, the communications interface 410D may provide voiceand/or data communications functionality in accordance a number ofwireless protocols. Examples of wireless protocols may comprise variouswireless local area network (WLAN) protocols, including the Institute ofElectrical and Electronics Engineers (IEEE) 802.xx series of protocols,such as IEEE 802.11a/b/g/n, IEEE 802.16, IEEE 802.20, and so forth.Other examples of wireless protocols may comprise various wireless widearea network (WWAN) protocols, such as GSM cellular radiotelephonesystem protocols with GPRS, CDMA cellular radiotelephone communicationsystems with 1×RTT, EDGE systems, EV-DO systems, EV-DV systems, HSDPAsystems, and so forth. Further examples of wireless protocols maycomprise wireless personal area network (PAN) protocols, such as anInfrared protocol, a protocol from the Bluetooth Special Interest Group(SIG) series of protocols, including Bluetooth Specification versionsv1.0, v1.1, v1.2, v2.0, v2.0 with Enhanced Data Rate (EDR), as well asone or more Bluetooth Profiles, and so forth. Yet another example ofwireless protocols may comprise near-field communication techniques andprotocols, such as electro-magnetic induction (EMI) techniques. Anexample of EMI techniques may comprise passive or active radio-frequencyidentification (RFID) protocols and devices. Other suitable protocolsmay comprise Ultra Wide Band (UWB), Digital Office (DO), Digital Home,Trusted Platform Module (TPM), ZigBee, and so forth.

In some embodiments, the controller 410 of the system 400 may comprise asystem bus 410E that couples various system components including theprocessor 410A, the memory 410B, and the I/O interface 410C. The systembus 410E can be any of several types of bus structure(s) including amemory bus or memory controller, a peripheral bus or external bus,and/or a local bus using any variety of available bus architecturesincluding, but not limited to, 9-bit bus, Industrial StandardArchitecture (ISA), Micro-Channel Architecture (MSA), Extended ISA(EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB),Peripheral Component Interconnect Card International Association Bus(PCMCIA), Small Computers Interface (SCSI) or other proprietary bus, orany custom bus suitable for computing device applications.

The controller 410 is connected to at least one optical detector 402, aswell as the plurality of motors 404, decoder 406 and trigger sensor 408,respectively. In some embodiments, the controller 410 may also comprisea programmable light source. In some embodiments, the controller 410 mayalso comprise a local display and a control panel. The controller 410can be connected to a local or a remote computer 414 through thecommunication interface 410D. The computer 414 can be then connected toa display 412 to configure scan recipe, program analysis parameters,display raw data, reconstructed images, and user interfaces of softwareprograms 416. The software program 416 for data analysis will be furtherdiscussed in detail in FIG. 5 .

FIG. 5 illustrates a flowchart of a method 500 of defect inspection of asubstrate surface, in accordance with some embodiments of the presentdisclosure. It is understood that additional operations may be providedbefore, during, and after the method 500 of FIG. 5 , and that someoperations may be omitted or reordered.

The method 500 starts with operation 502 in which a substrate isprovided according to some embodiments. In some embodiments, thesubstrate is provided to an inspection station 104 after a semiconductormanufacturing process conducted in a processing station 102. Examples ofthe semiconductor manufacturing process include cleaning,photolithography, wet etching, dry etching, dielectric deposition, metaldeposition, and processes known in the art. In some embodiments, thesubstrate contains at least one feature including a metal contact, etchtrench, an isolation, an interconnect line and the like. In someembodiments, the at least one feature also includes a hole.

In some embodiments, the inspection system 104 includes a transportsystem (e.g., a conveyor or a pair of tracks), a line scan camera, and alocal computer with a storage unit and a display unit. In someembodiments, the transport system can be used to transport thesubstrate. In some other embodiments, the transport system can be usedto transport the line scan camera.

In some embodiments, the inspection system 104 comprises a pair oftracks 122A and 122B that guide a movement of an optical detector 130 ina first horizontal direction (i.e., X-direction), and a track 124 thatguides a movement of the optical detector 130 in a second horizontaldirection (i.e., Y-direction) that is normal to the first horizontaldirection (e.g., X-direction). In some embodiments, the optical detector130 is a line scan camera. The X-Y plane can be parallel to the plane ofa stage 132, on which a part to be inspected can be placed. Motors 126and 128 provide linear movements in the X- and Y-direction such that theoptical detector 130 in the X-Y plane can scan the surface of a wafer(not shown) on the stage 132. In some embodiments, the optical detector130 can also move in a third vertical direction (e.g., Z-direction) thatis perpendicular to the X-Y plane on a track 134 controlled by a motor126. In some embodiments, the motors 126, 128, and 136 can be linearelectric motors providing high speed linear motion and accurate positioncontrol of the optical detector 130.

In some embodiments, a plurality of optical detectors 130 can be used toscan complex surfaces to simultaneously scan multiple wafers or multiplelocations on a same surface. In some other embodiments, the wafer underinspection can be moved on a conveyor stage/a robot arm, while theoptical detector 130 is fixed.

In some embodiments, instead of capturing an image of the entire waferas a whole, the line scan camera 202 collects image data one scan lineat a time. An image line 212, indicated by a short dashed line in FIG.2A, is a line region where the reflected or scattered light from thesurface of the wafer under inspection is collected by a light sensor inthe line scan camera 202 through the imaging lens 203. In someembodiments, the field of view 218 of the line scan camera 202 in the Ydirection, e.g., the maximum length of the image line 212, can beadjusted by the width of the light sensor in the line scan camera 202,the working distance 209, and the focal length of the lens 203. In someembodiments, the image line 212 is the overlap portion of the field ofview 218 in Y direction and the surface of the wafer 206. For example,the width of imaging lens can be 25 millimeters (mm), which can providea field of view 218 with a width of up to 215 mm in the Y direction anda sensor width of 14 mm. Therefore, the resolution in the Y direction,which has a unit in mm per pixel for a light sensor width of 1024 pixelsper line, can be controlled by the working distance 209 taking intoaccount the diameter of the wafer 206. In some other embodiments, theline scan cameras comprising light sensors with different width andnumbers of pixels can be used and are within the scope of thisdisclosure. In some embodiments, the resolution that such system canprovide is 9 micrometer.

In some embodiments, the line scan camera 202 includes a light sensorthat can be based on a variety of technologies such as, for example, acharge-coupled detector (CCD), a complementary metal-oxide-semiconductor(CMOS), or a hybrid CCD/CMOS architecture. In some embodiments, thelight sensor can be a mono or color sensor. In some embodiments, suchlight sensor can be configured to either work in a broad range ofwavelengths or a narrow range of wavelengths e.g., ultraviolet light,visible light, infrared light, x-ray and/or other appropriatewavelengths. In some other embodiments, such light sensor can beconfigured to receive either reflected and/or scattered non-fluorescencelight from a light source or a fluorescence light emitted by the defectsor features due to an excitation by the light source.

In some embodiments, the substrate 206 includes a silicon substrate.Alternatively, the wafer 206 may include other elementary semiconductormaterial such as, for example, germanium. The substrate may also includea compound semiconductor material such as silicon carbide, galliumarsenide, indium arsenide, and indium phosphide. Furthermore, the wafer206 may include an alloy semiconductor material such as silicongermanium, silicon germanium carbide, gallium arsenic phosphide, andgallium indium phosphide. Each material may interact differently withthe incident light from the light source due to different materialproperties, e.g., refractive index and extinction coefficient, which canaffect the design of the illumination source and the light sensor, e.g.,wavelength, sensitivity and mode (e.g., scattered, reflected light orfluorescence light), as well as the speed of the conveyor.

The method 500 continues to operation 504 in which scan parameters areconfigured according to some embodiments. In some embodiment, thisconfiguration includes a process of writing an inspection recipe orrecalling an existing recipe to an inspection operation, which containsinspection system parameter settings for a particular type of substrate,feature, or defect to be inspected. In some embodiments, operation 604also includes configuration of the controller 410 which controls themotion of the line scan camera 130 relative to the substrate, e.g.,speed and direction. In some embodiments, inspection parameters includetrigger criteria, inspection resolution, line frequency, pixelfrequency, total acquisition time, illumination intensity, moving speedof the linear motors 124/126/136, speed of the conveyor 210, size of thesubstrate 206, and/or other suitable parameters.

The method 500 continues to operation 506 in which the substrate isscanned by a line scan camera in according to some embodiments. In someembodiments, the substrate is scanned by the line scan camera, whilebeing transported by the conveyor at a constant speed along a directionperpendicular to the line scan direction, as discussed above withrespect to FIGS. 2 and 3 , for example. In some embodiments, the linescanning can be triggered by the controller 410 which acquires positionparameters from the encoder located on the conveyor. In some otherembodiments, the substrate is held steady on the stage 132 and scannedby the line scan camera which is transported on a pair of tracks 122along the direction perpendicular to the line scan direction, asdiscussed in FIG. 1B.

The method 500 continues to operation 508 in which a plurality of linescan images are recorded by the line scan camera according to a scanningprocess illustrated in FIG. 3 . In some embodiments, each of theplurality of line scan images obtained from the line scan camera isrecorded together with corresponding position (e.g., X-, Y- andZ-coordinates).

The method 500 continues with operation 510 in which a sample image isreconstructed according to some embodiments. In some embodiments, theplurality of line scan images is converted from analog signals todigital signals and stored in a local computer, followed by operation508, during which a sample image is reconstructed based on the pluralityof line scan images and preprocessed once a scanning of the surface ofthe first wafer is completed. In some embodiments, operation 510includes at least one of the processes such as, for example, offsetcorrection, gain correction, distortion correction, adjusting contrast,and the like. In some embodiments, the preprocessed sample image can bedisplayed on a local display monitor which is coupled to a localcomputer. In some embodiments, the display monitor can be also a touchscreen for inputting and displaying inspection parameters.

In some embodiments, the line speed of the line scan camera isdetermined by the speed of the conveyor. In another embodiment, theresolution requirement of the line scan camera can be determined by thetype of defects that are interested or are potentially introduced in arespective step of the manufacturing production line.

The method 500 continues with operation 512 in which a last position isdetermined according to some embodiments. When the position is not thelast position for performing a line scan, the method 500 continues withoperations 508 and 510, wherein a plurality of line scan images arecollected a second position. When the position is determined as the lastposition for performing a line scan on the substrate, the method 500continues with operation 514, in which the scan is terminated, acomplete surface data is loaded onto the local computer.

The method 500 continues with operation 516 in which post-processingfunctions can be selected for quantitative analysis of the surfacefeatures according to some embodiments. Functions include but are notlimited to, measurement of diameter, roundness, raw edge, consumption,contamination and the like.

FIGS. 6A-6D illustrate schematics of a hole feature during apost-processing analysis, in accordance with some embodiments of thepresent disclosure. In some embodiments, the post-processing analysisfits a theoretical circle to the hole feature. In some embodiments, thepost-processing analysis determines the center 602 of a theoreticalcircle and the radius 604 (Rtheory) of the theoretical circle, accordingto a predetermined algorithm. In some embodiments, the hole feature 600comprises defects 606 on the edge, i.e., a first defect 606-1, a seconddefect 606-2, a third defect 606-3, and a fourth defect 606-4. In theillustrated embodiment, the distance (Rreal) between the actual edge ofthe hole feature at the first defect 606-1 or the fourth defect 606-4and the center 602 of the theoretical hole is less than the radius 604of the theoretical circle, i.e., Rreal<Rtheory or ΔR=Rreal−Rtheory<0.Similarly, in the illustrated embodiment, the distance between theactual edge of the hole feature at the second defect 606-2 or the thirddefect 606-3 and the center 602 of the theoretical circle is greaterthan the radius 604 of the theoretical circle model, i.e., Rreal>Rtheoryor ΔR=Rreal−Rtheory>0. In some embodiments, the roundness is defined asbelow

${Roundness} = \frac{\sqrt{\sum\left( {R_{real} - R_{thoery}} \right)^{2}}}{N}$wherein N is the number of measurements that are made and is a positiveinteger, e.g. N=1000, where Rreal is measured.

Using the third defect 606-3 and the fourth defect 606-4 as examples,Rreal 612-1 of the third defect 606-3 is greater than Rtheory 604 andthe difference between Rreal 612-1 and Rtheory 604 is thus a positivevalue. Similarly, the Rreal 612-2 of the fourth defect 606-4 is lessthan Rtheory 604 and the difference between Rreal 612-2 and Rtheory 604is a negative value.

In the illustrated embodiments, the absolute values of ΔR 622 inmicrometer at each position of the edge of the hole feature can beplotted against the radian 624 in degree. In some embodiments, ΔR 622 isalso known as a contamination value. Four peaks 626-1, 626-2, 626-3 and626-4 correspond to the first defect 606-1, the second defect 606-2, thethird defect 606-3 and the fourth defect 606-4. In the illustratedembodiments, the ΔR values 622 of the four defects are all greater than10 micrometer. The angle (θ) 628-1, 628-2, 628-3 and 628-4 ofcorresponding peaks 626-1, 626-2, 626-3 and 626-4 at a ΔR 622 value of10 micrometer can be then determined, which can be further used todetermine the arc length (S) of the corresponding defects can bedetermined using the equation below

$S = {R_{real}\frac{\pi\theta}{180}}$wherein S is the arc length at the corresponding defects in micrometer,R is the radius in micrometer, and θ is the angle in degree.

A raw edge length is determined using the equation belowD_(raw,sum)=ΣS

In the illustrated embodiment, Draw,sum=S1+S2+S3+S4, wherein S1, S2, S3,S4 are the arc length of defects at ΔR 622 value of 10 micrometer.

Further, a raw edge ratio can be determined using the equation below

${{Rati}o_{{raw}\mspace{14mu}{edge}}} = \frac{D_{{raw},{sum}}}{C}$wherein C is the circumference in micrometer of the theoretical circlemodel. The raw edge ratio is used to determine the arc length of defectsthat is over a threshold value (e.g., ΔR 522 value of 10 micrometer). Asillustrated in FIG. 6D, three defects 632, 634 and 636 arehypothetically configured separately in a hole feature 600. Assuming ΔR522 values of the three defects are greater than 10 micrometers. The arclength of the defect 632 is greater than the arc length of the defect634, which is greater than the arc length of the defect 636. Therefore,the raw edge ratio of the defect 632 is greater than the raw edge ratioof the defect 634, which is greater than the raw edge ratio of thedefect 636.

In some embodiments, a consumption value of an under-formed hole feature642 (e.g., under etched during an etching process or under developedduring a photolithography process) is determined by the differencebetween the top surface 644 of the hole feature and position 646 of thehole feature 642.

FIG. 7 illustrates a user interface 700 of a software program that isused for post-processing surface images, in accordance with someembodiments of the present disclosure. A user can use this interface todefine post-processing analysis threshold values to determine if asurface fails which needs to be reprocessed or passes which can befurther processed in following processes. In the illustrated embodiment,the user interface 700 allows user to specify the roundness value 702,ΔR value 704 for determining Raw edge length, raw edge ratio706/708/710, contamination value 712 and pixel calibration ratio 714.

In one embodiment, the pixel calibration ratio 714 corresponds to eachpixel of the camera and is calculated based on a calibration sheet and amachine, e.g. an acrylic fixture. For example, an image calibration maystart after a calibration sheet is placed in the center of the acrylicfixture, and may include: taking a calibration image, drawing a straightline to calculate a ratio between the pixel and the length, and savingit as the pixel calibration ratio 714. In one embodiment, after clickingto start image calibration, the motor will move to the center of theacrylic fixture. Then a clear calibration scale can be found using amotor control page. Then an image is taken and the system automaticallyswitches to the image calculation tab. One can use a pull line toroughly draw a straight line of a fixed length, with the starting pointand the end point on the same side of the scale. After zooming in, onecan use the pull line function to adjust the positions of the startingpoint and/or the end point. After the scale reading on the calibrationsheet is entered, the system can calculate the image calibration ratioand store it as the pixel calibration ratio 714.

The preceding merely illustrates the principles of the disclosure. Itwill thus be appreciated that those of ordinary skill in the art will beable to devise various arrangements which, although not explicitlydescribed or shown herein, embody the principles of the disclosure andare included within its spirit and scope. Furthermore, all examples andconditional language recited herein are principally intended expresslyto be only for pedagogical purposes and to aid the reader inunderstanding the principles of the disclosure and the inventiveconcepts, and are to be construed as being without limitation to suchspecifically recited examples and conditions. Moreover, all statementsherein reciting principles, aspects, and embodiments of the disclosure,as well as specific examples thereof, are intended to encompass bothstructural and functional equivalents thereof. Additionally, it isintended that such equivalents include both currently known equivalentsand equivalents developed in the future, i.e., any elements developedthat perform the same function, regardless of structure.

This description of the exemplary embodiments is set to be understood inconnection with the figures of the accompanying drawing, which are to beconsidered part of the entire written description. In the description,relative terms such as “lower,” “upper,” “horizontal,” “vertical,”“above,” “below,” “up,” “down,” “top” and “bottom” as well asderivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,”etc.) should be construed to refer to the orientation as then describedor as shown in the drawing under discussion. These relative terms arefor convenience of description and do not require that the apparatus beconstructed or operated in a particular orientation.

Although the disclosure has been described in terms of exemplaryembodiments, it is not limited thereto. Rather, the appended claimsshould be construed broadly, to include other variants and embodimentsof the disclosure, which may be made by those of ordinary skill in theart without departing from the scope and range of equivalents of thedisclosure.

In an embodiment, a method for defect detection in a hole array on asubstrate, includes: scanning a substrate surface using at least oneoptical detector, generating at least one image of the substratesurface; and analyzing the at least one image to detect defects in thehole array on the substrate surface based on a set of predeterminedcriteria.

In another embodiment, an inspection station for defect detection in ahole array on a substrate, includes: an optical detector configured toscan a substrate surface and generate at least one image of thesubstrate surface; a transport mechanism configured to transport theoptical detector so as to scan the substrate surface; and at least oneprocessor configured to receive the at least one image from the opticaldetector and analyze the at least one image to detect defects on thesubstrate surface based on a set of pre-determined criteria.

Yet, in another embodiment, a system for defect detection in a holearray on a substrate, includes: a first processing station forperforming a first semiconductor manufacturing process; a secondprocessing station for performing a second semiconductor manufacturingprocess; an inspection station coupled between the first and the secondprocessing station for transporting the substrate between the first andthe second processing stations, wherein the inspection stationcomprises: an optical detector configured to scan a substrate surfaceand generate at least one image of the substrate surface; a transportmechanism configured to transport the optical detector so as to scan thesubstrate surface; and at least one processor configured to receive theat least one image from the optical detector and analyze the at leastone image to detect defects on the substrate surface based on a set ofpre-determined criteria.

The foregoing outlines features of several embodiments so that thoseordinary skilled in the art may better understand the aspects of thepresent disclosure. Those skilled in the art should appreciate that theymay readily use the present disclosure as a basis for designing ormodifying other processes and structures for carrying out the samepurposes and/or achieving the same advantages of the embodimentsintroduced herein. Those skilled in the art should also realize thatsuch equivalent constructions do not depart from the spirit and scope ofthe present disclosure, and that they may make various changes,substitutions, and alterations herein without departing from the spiritand scope of the present disclosure.

In this document, the term “module” as used herein, refers to software,firmware, hardware, and any combination of these elements for performingthe associated functions described herein. Additionally, for purpose ofdiscussion, the various modules are described as discrete modules;however, as would be apparent to one of ordinary skill in the art, twoor more modules may be combined to form a single module that performsthe associated functions according embodiments of the invention.

A person of ordinary skill in the art would further appreciate that anyof the various illustrative logical blocks, modules, processors, means,circuits, methods and functions described in connection with the aspectsdisclosed herein can be implemented by electronic hardware (e.g., adigital implementation, an analog implementation, or a combination ofthe two), firmware, various forms of program or design codeincorporating instructions (which can be referred to herein, forconvenience, as “software” or a “software module), or any combination ofthese techniques. To clearly illustrate this interchangeability ofhardware, firmware and software, various illustrative components,blocks, modules, circuits, and steps have been described above generallyin terms of their functionality. Whether such functionality isimplemented as hardware, firmware or software, or a combination of thesetechniques, depends upon the particular application and designconstraints imposed on the overall system. Skilled artisans canimplement the described functionality in various ways for eachparticular application, but such implementation decisions do not cause adeparture from the scope of the present disclosure.

Furthermore, a person of ordinary skill in the art would understand thatvarious illustrative logical blocks, modules, devices, components andcircuits described herein can be implemented within or performed by anintegrated circuit (IC) that can include a general purpose processor, adigital signal processor (DSP), an application specific integratedcircuit (ASIC), a field programmable gate array (FPGA) or otherprogrammable logic device, or any combination thereof. The logicalblocks, modules, and circuits can further include antennas and/ortransceivers to communicate with various components within the networkor within the device. A general purpose processor can be amicroprocessor, but in the alternative, the processor can be anyconventional processor, controller, or state machine. A processor canalso be implemented as a combination of computing devices, e.g., acombination of a DSP and a microprocessor, a plurality ofmicroprocessors, one or more microprocessors in conjunction with a DSPcore, or any other suitable configuration to perform the functionsdescribed herein.

Conditional language such as, among others, “can,” “could,” “might” or“may,” unless specifically stated otherwise, are otherwise understoodwithin the context as used in general to convey that certain embodimentsinclude, while other embodiments do not include, certain features,elements and/or steps. Thus, such conditional language is not generallyintended to imply that features, elements and/or steps are in any wayrequired for one or more embodiments or that one or more embodimentsnecessarily include logic for deciding, with or without user input orprompting, whether these features, elements and/or steps are included orare to be performed in any particular embodiment.

Additionally, persons of skill in the art would be enabled to configurefunctional entities to perform the operations described herein afterreading the present disclosure. The term “configured” as used hereinwith respect to a specified operation or function refers to a system,device, component, circuit, structure, machine, etc. that is physicallyor virtually constructed, programmed and/or arranged to perform thespecified operation or function.

Disjunctive language such as the phrase “at least one of X, Y, or Z,”unless specifically stated otherwise, is otherwise understood with thecontext as used in general to present that an item, term, etc., may beeither X, Y, or Z, or any combination thereof (e.g., X, Y, and/or Z).Thus, such disjunctive language is not generally intended to, and shouldnot, imply that certain embodiments require at least one of X, at leastone of Y, or at least one of Z to each be present.

It should be emphasized that many variations and modifications may bemade to the above-described embodiments, the elements of which are to beunderstood as being among other acceptable examples. All suchmodifications and variations are intended to be included herein withinthe scope of this disclosure and protected by the following claims.

What is claimed is:
 1. A method for defect detection in a hole array ona substrate, comprising: scanning a substrate surface using at least oneoptical detector, generating at least one image of the substratesurface; and analyzing the at least one image to detect defects in thehole array on the substrate surface based on a comparison between atleast one first distance and a second distance, wherein the at least onefirst distance is determined based on at least one actual edge of thehole array and a center of a theoretical hole model, and the seconddistance is determined based on a radius of the theoretical hole model.2. The method of claim 1, wherein the scanning further comprises:transporting the at least one optical detector using a transportmechanism.
 3. The method of claim 2, wherein the transport mechanismcomprises at least one linear motor.
 4. The method of claim 1, whereineach of the at least one optical detector comprises a line scan camera,wherein the line scan camera scans the substrate surface one pixel lineat a time.
 5. The method of claim 1, wherein the generating furthercomprises: providing pixel data from the optical detector to a localprocessor coupled to the optical detector; generating the at least oneimage of the substrate surface by processing the pixel data; anddisplaying the at least one image of the substrate surface on a displaymonitor coupled to the local processor.
 6. The method of claim 1,further comprising: illuminating the wafer surface using a light source.7. The method of claim 6, wherein the light source comprises a linelight source that only illuminates a line portion of the substratesurface at one time.
 8. An inspection station for defect detection in ahole array on a substrate, comprising: at least one optical detectorconfigured to scan a substrate surface and generate at least one imageof the substrate surface; a transport mechanism configured to transportthe at least one optical detector so as to scan the substrate surface;and at least one processor configured to receive the at least one imagefrom the at least one optical detector and analyze the at least oneimage to detect defects on the substrate surface based on a comparisonbetween at least one first distance and a second distance, wherein theat least one first distance is determined based on at least one actualedge of the hole array and a center of a theoretical hole model, and thesecond distance is determined based on a radius of the theoretical holemodel.
 9. The system of claim 8, wherein each of the at least oneoptical detector comprises a line scan camera, wherein the line scancamera scans the substrate surface one pixel line at a time.
 10. Thesystem of claim 8, wherein the transport mechanism comprises at leastone linear motor.
 11. The system of claim 8, further comprising: a lightsource to illuminate the wafer surface.
 12. The system of claim 11,wherein the light source comprises a line light source that onlyilluminates a line portion of the wafer surface at one time.
 13. Thesystem of claim 8, wherein each of the at least one processor isconfigured to: receive a pixel data from the at least one opticaldetector; preprocess the pixel data to regenerate the at least one imageof the substrate surface; and display the at least one image of thesubstrate surface on a display monitor.
 14. The system of claim 8,wherein the at least one processor is further configured to: receive theat least one image of the substrate surface; and analyze the at leastone image of the substrate surface.
 15. A system for defect detection ina hole array on a substrate, comprising: a first processing station forperforming a first semiconductor manufacturing process; a secondprocessing station for performing a second semiconductor manufacturingprocess; an inspection station coupled between the first and the secondprocessing station for transporting the substrate between the first andthe second processing stations, wherein the inspection stationcomprises: at least one optical detector configured to scan a substratesurface and generate at least one image of the substrate surface; atransport mechanism configured to transport the at least one opticaldetector so as to scan the substrate surface; and at least one processorconfigured to receive the at least one image from the at least oneoptical detector and analyze the at least one image to detect defects onthe substrate surface based on a comparison between at least one firstdistance and a second distance, wherein the at least one first distanceis determined based on at least one actual edge of the hole array and acenter of a theoretical hole model, and the second distance isdetermined based on a radius of the theoretical hole model.
 16. Thesystem of claim 15, wherein each of the at least one optical detectorcomprises a line scan camera, wherein the line scan camera scans thesubstrate surface one pixel line at a time.
 17. The system of claim 15,wherein the transport mechanism comprises at least one linear motor. 18.The system of claim 15, further comprising: a light source to illuminatethe substrate surface, wherein the light source comprises a line lightsource that only illuminates a line portion of the substrate surface atone time.
 19. The system of claim 15, wherein each of the at least oneprocessor is configured to: receive a pixel data from the at least oneoptical detector; preprocess the pixel data to obtain the at least oneimage of the substrate surface; and display the at least one image ofthe substrate surface on a display monitor.
 20. The system of claim 15,wherein the at least one processor is further configured to: receive theat least one image of the substrate surface; and analyze the at leastone image of the substrate surface.